| ISBN: ISBN: 0-7695-0078-1
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| ISBN: DOI: 10.1109/DATE.1999.761206
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| |
| description |
The paper introduces the new concept of symmetric transparent BIST
for RAMs. This concept allows to skip the signature prediction phase
of conventional transparent BIST approaches and therefore yields a
significant reduction of test time. The hardware cost and the fault
coverage of the new scheme remain comparable to that of a
traditional transparent BIST scheme. In many cases, experimental
studies even show a higher fault coverage obtained in shorter test
time.
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| publisher |
Institute of Electrical and Electronics Engineers
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| type |
Text
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| Article in Proceedings
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| source |
In: Proceedings of the 2nd Conference on Design, Automation and Test
in Europe (DATE), Munich, Germany, March 9-12, 1999, pp. 702-708
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| contributor |
Rechnerarchitektur (IFI)
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| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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